1. Field of the Invention
The present invention relates to packaging techniques for semiconductor dies. More specifically, the present invention relates to packaging techniques for coupling memory devices with single-chip and/or multi-chip modules that include semiconductor dies that communicate signals using proximity connectors.
2. Related Art
In many existing computer systems, computational performance is often limited by a latency and/or bandwidth of interconnects between one or more processors, such as a central processing unit (CPU), and main memory. The latency and/or bandwidth may depend on variables such as packaging, connectors, and/or a printed circuit board or motherboard. In order to obtain a high-performance system, expensive and complicated components, such as a motherboard having multiple layers and a narrow critical dimension for wires, are often used. In addition, many systems include one or more cache memories proximate to the CPU to improve performance. Nonetheless, the main memory is often located a significant distance from the CPU and communication over this distance often occurs via a high-frequency data bus, which may limit performance.
Researchers have begun to investigate alternative techniques for communicating between semiconductor dies or chips. One promising technique involves integrating arrays of capacitive transmitters and receivers onto semiconductor chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip, it becomes possible to transmit data signals directly from the first chip to the second chip without having to route the data signals through intervening signal lines within a printed circuit board.
Capacitively coupled inter-chip communication may offer a high-bandwidth when communicating between adjacent chips and chips that are in close proximity to one another. Latency challenges, however, may occur when communicating over longer distances, such as in a multiple-chip module (MCM). This latency may impact communication between a CPU and an external cache and/or main memory, and therefore, may adversely affect the system performance.
What is needed is needed are packaging techniques for coupling memory devices to semiconductor chips or dies that communicate inter-chip signals using capacitive or proximity connectors without the problems listed above.